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Silicon on Insulator (SOI) Wafer – Characteristics and Applications

  • icon2 July 26, 2016
  • icon3 WaferPro
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SOI (silicon-on-insulator) wafers are semiconductor substrate materials composed of a thin top silicon layer separated from the bulk silicon wafer by a silicon dioxide insulator layer. This fundamentally differentiated structure imbues SOI wafers with superior electrical performance compared to conventional silicon wafers.

Emergence of SOI Wafers

The inception of SOI wafer technology commenced in the 1960s, predicated predominately on augmenting the speed and diminishing the power consumption of integrated chips. Concerted development efforts by suppliers have enabled significant improvements in quality and reductions in fabrication costs.

SOI wafers have now pervaded a myriad of demanding applications including microprocessors, RF devices, MEMS devices, power devices, and more. Advancements in bonding and layer transfer technologies have also expanded the horizons of SOI wafer utility.

Structural Composition

SOI wafers are fabricated by sandwiching a silicon dioxide (SiO2) insulator layer between a thin top silicon device layer and a bulk silicon handle wafer.

Standard layer thicknesses are:

  • Device Silicon - 5nm to 2μm
  • Buried Oxide (BOX) - 10nm to 2μm
  • Handle Wafer - 525μm to 725μm

The disparity in silicon layer thicknesses isolates the device layer for markedly enhanced performance.

SOI Wafer Structure and Composition

Substrate Architecture

There are three fundamental elements which characterize the SOI wafer architecture:

  • Top silicon device layer - This ultra thin layer enables formation of active devices.
  • Buried oxide (BOX) layer - Electrically isolates the device layer.
  • Handle wafer - Provides mechanical strength and support.

This layered arrangement bestows SOI wafers with performance capabilities exceeding conventional bulk silicon wafers.

Silicon Device Layer Buried Oxide (BOX) Layer Handle Wafer
Active device formation Electrically isolates device layer Mechanical support
Ultra thin (5nm - 2μm) Silicon dioxide (10nm - 2μm) Thick (525μm - 725μm)

Fabrication Methodologies

There are a range of proven processes for fabricating SOI wafers:

  • SIMOX - Implantation of oxygen atoms into silicon and high temp annealing
  • BESOI - Bonding of oxidized handle to device wafer and split
  • Smart CutTM - Implantation of hydrogen to cleave topped handle wafer

Each approach has relative merits in terms of quality and cost. Smart CutTM has enabled high volume production crucial for supporting the latest device generations.

Smart CutTM Process

The Smart CutTM process catalyzed the rapid adoption of SOI wafers. It revolutionized SOI fabrication via the introduction of hydrogen ion implantation to cleave thin device layers.

The key benefits of Smart CutTM include:

  • Ultra thin uniform device layers
  • High quality buried oxide layers
  • Cost effective volume manufacturing
  • Substrate thickness and layer optimization

Customization Capabilities

SOI wafer attributes can be tailored to meet the exacting needs of cutting edge devices through:

  • Silicon device layer thickness tuning
  • Buried oxide thickness adjustment
  • Handle wafer resistivity modification
  • Layer uniformity enhancement

This enables fully customized wafers for maximal device performance.

Advantages of SOI Wafers

Electrical Isolation

The buried oxide layer in SOI wafers provides complete electrical isolation between the handle wafer and device layer. This Noticeably ameliorates device performance by:

  • Eliminating latchup - Stops parasitic bipolar transistor formation
  • Reducing leakage current - Minimizes current flow through substrate
  • Lowering capacitance - Mitigates charge accumulation slowing circuits
  • Preventing radiation induced errors
  • Enabling simpler device isolation techniques

Reduced Short Channel Effects

As integrated circuits have become more dense, channel lengths shortened substantially. This has exacerbated deleterious short channel effects including threshold voltage roll off and drain induced barrier lowering.

However, the thin device layer of SOI devices significantly suppresses short channel effects. This bolsters electrical control and facilitates further scaling.

Other Key Benefits

Additional advantages stem from the SOI wafer structure:

  • Lower power consumption - Reduced parasitic losses cut IC power draw
  • Faster speeds - Lower capacitances enable greater switching speeds
  • Higher densities - Compact isolation enables packing more devices
  • Enhanced reliability and yield - Effects of defects and variations localized
  • Multi-gate and 3D device support

SOI Wafer Manufacturing Process

Fabrication Overview

SOI wafer manufacturing entails an intricate fabrication procedure necessitating state-of-the-art facilities.

The main process steps include:

  • Silicon ingot growth
  • Wafer slicing
  • CMP planarization
  • Thermal oxidation
  • Device/handle layer preparation
  • Bonding and layer transfer
  • Finish metrology

Wafer diameter has progressed to 300mm to augment productivity. Automation has also been vital for high volume, low cost manufacturing.

Standards and Specifications

To satisfy escalating quality requisites, we stringently adhere to industry norms including:

  • SEMI standards - Ensures benchmark wafer specifications
  • Materials characterization - Confirms purity and composition
  • Dimensional tolerances - Guarantees thickness uniformity
  • Surface Finish - Minimizes roughness and defects
  • Cleanliness - Limits contaminants to parts per trillion

Quality Control Testing

To affirm our SOI wafers surpass expectations, our battery of QC assessments includes:

  • Surface scanning - Detects defects and irregularities
  • Haze measurements - Evaluates surface quality
  • Bow and warp evaluation - Checks dimensional stability
  • Resistivity and thickness profiling - Validates intra-wafer uniformity

Our proprietary statistical process control methodology fortifies quality.

Flexible Volume Production

Leveraging our advanced manufacturing infrastructure, we can provide SOI wafers over a broad range of volumes tailored to your specific requirements with short lead times including:

  • R&D and prototyping
  • Pilot production runs
  • High volume manufacturing

Characterization and Properties of SOI Wafers

Structural Characteristics

Sophisticated materials characterization is imperative for correlating SOI structural properties to device performance.


We rigorously appraise thickness uniformity across the wafer and within die using scanning electron microscopy and eddy current sensors.

Our SOI wafer thickness variation is constrained to ± 2.5% 3σ.


Utilizing scan test microscopy and crystal-originated particle mapping, our SOI wafer defects per area are confined to:

  • <= 0.03 cm2 for >= 0.13μm size
  • <= 0.01 cm2 for >= 0.17μm size

Surface Roughness

Applying atomic force microscopy, we restrict Ra surface roughness to <= 0.5nm. This fortifies device yield by circumventing lithography issues.


Based on laser interferometry measurements, our SOI wafer flatness, Sa, is less than 30nm over the entire 300mm diameter. This guarantees multi-layer alignment accuracy.

Additional Properties

Further metrics confirmed with analytical techniques include:

  • Elemental impurities (SRP, GDMS) - Validate purity
  • Crystallinity (HRXRD) - Ensures perfect silicon lattice
  • Wafer Resistivity - Optimized 10-100 Ω-cm to attenuate losses
  • Charging (KPFM) - Minimizes charge accumulation

Applications of SOI Wafers

The superlative electrical isolation and reduced parasitic capacitances associated with SOI wafer devices confer definitive performance gains, cementing their standing across manifold high value sectors:


The thin buried oxide enables aggressive transistor scaling and dense packing culminating in momentous leaps in computer processing capabilities:

  • Intel Sandy Bridge - First high volume CPU on 32nm node
  • AMD RyzenTM - Breakthrough SOI enabled desktop processor
  • IBM z15 - Industry leading transaction processing

RF Devices

The insulating substrate architecture of SOI significantly bolsters RF integrated circuit attributes:

  • Lower losses - Mitigates power dissipation
  • Reduced noise/interference - Lessens signal corruption
  • Higher operating bandwidths and frequencies
  • Better linearity and dynamic range

Enabling a new echelon of fast, efficient wireless connectivity.

MEMS Devices

SOI wafers have become pervasive for MEMS transducers taking advantage of:

  • Exceptional electromechanical properties - Responsiveness
  • Flexible structure - Facilitates moving element etching
  • Wafer level encapsulation option

Underpinning everything from accelerometers to micro-mirror arrays.

Power Devices

SOI technology has unlocked substantially upgraded power semiconductor devices:

  • Lower conduction losses - Enhances electrical efficiency
  • Faster switching speeds - Enables high frequency operation
  • Higher temperature capabilities
  • Simplified thermal management


Leveraging the buried oxide layer for optical confinement and guiding, SOI wafers have become the platform of choice for silicon photonics:

  • Waveguides - Route optical signals on chip
  • Optical modulators - Encode data on light waves
  • Photodetectors - Convert photons to electrons

Quantum Computing

Exploiting quantum mechanical phenomena for computation necessitates a substrate conducive to delicately generating and detecting quantum states. SOI delivers:

  • Noise isolation - Preserves quantum coherence
  • Low defect interface - Mitigates qubit decoherence
  • CMOS compatible - Allows co-integration control electronics

Comparison of SOI Wafers to Bulk Silicon Wafers

While bulk silicon wafers just utilize a single substrate layer, SOI wafers incorporate a trilayer structure delivering differentiated capabilities:

Bulk Silicon Wafer SOI Wafer
Structure Single monolithic substrate Silicon device/buried oxide/bulk silicon handle layers
Parasitic Losses High - current leaks through substrate Extremely low - insulated device layer
Power Consumption Higher - losses diminish efficiency Lower - mitigates power drain
Speed Reduced - high capacitance Very fast - low capacitance
Device Density Lower - larger isolation regions Higher - compact isolation

This directly translates to markedly augmented performance across a panoply of contemporary device applications where SOI is supplanting bulk silicon.

Future Outlook and Developments in SOI Wafer Technology

Evolving Applications

SOI wafer utilization continues expanding into additional specialized sectors:

  • Automotive - Demanding reliability/safety needs
  • Aerospace - Radiation hardening
  • IoT/wearables - Ultra low power
  • Deep learning accelerators - Parallelism

Technical Improvements

Ongoing research and development is engendering multiple enhancements:

  • Ultra-thin 3nm device layers
  • Further reduced buried oxide roughness
  • Advanced substrates (GaN-on-SOI)
  • Higher resistivity handle wafers

Manufacturing Innovation

Process evolution is also cutting costs and increasing availability:

  • 450mm diameter wafers - Improves productivity
  • Automation - Enables high volume supply chains
  • Direct bonding - Simplifies layer transfer

SOI wafer technology is poised to continue redefining electronics performance benchmarks through impactful improvements meeting contemporary design challenges. Our steadfast commitment to pushing SOI wafer capabilities to the limits ensures customers always have access to the most cutting edge solutions.


What are some key benefits of SOI wafers?

SOI wafers offer several major advantages over conventional bulk silicon wafers:

Higher Performance

  • Increased speed: Up to 35% faster operation via reduced parasitic capacitances
  • Lower power consumption: Leakage currents eliminated enabling up to 30% less power draw
  • Higher density: More compact isolation enables greater transistor density

Greater Reliability

  • Total isolation removes latchup: Prevents electrical faults
  • Radiation resistance: Immune to single event upsets for aerospace and automotive use

Enhanced linearity, less noise, and higher fmax for analog/RF ICs

What are some common SOI applications?


  • Intel, AMD, Apple: Leading edge CPU performance
  • IBM z Systems: Commercial transaction speed records

RF and Analog ICs

  • 5G mmWave: High frequency wireless connectivity
  • GPS, radar and sensors: Precision mixed signal

Power Devices

  • Automotive systems
  • Industrial motor drives
  • Renewable energy conversion

Photonics and Quantum Computing

  • Photonic integrated circuits
  • Quantum dots and qubits

How does the SOI fabrication process work?

Smart CutTM Process

The breakthrough Smart CutTM method catalyzed SOI adoption via implantation and layer transfer:

  1. Oxidize and implant hydrogen into donor handle wafer
  2. Flip and directly bond to device wafer
  3. Cleave implanted region transferring top donor layer
  4. CMP polish device wafer and oxidize BOX
  5. Fabricate devices in ultra thin top silicon layer


  • Cost effective volume manufacturing
  • Tunable device layer thickness
  • Advanced layer transfer technology
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