What are P type and N type Silicon Wafers?

• January 10, 2024
• WaferPro
• 0

Silicon wafers are the foundation of modern electronics. From computers to smartphones to solar panels, silicon wafers enable all the technological innovations we rely on today. But not all silicon wafers are created equal. The two main categories of silicon wafers are P type and N type. If you come to this web page and you are looking to buy P type silicon wafers or N type silicon wafers online, you can check out WaferPro's shop page here.

The basics of P type silicon and N type silicon

Silicon in its pure form is actually not a very good conductor of electricity. To make it useful for electronics, tiny amounts of specific impurities need to be added in a process called doping. The two options for doping are elements from group III and group V of the periodic table.

P type silicon is created when group III elements like boron or gallium are used as the doping agent. The addition of these elements causes the silicon to have an abundance of positive charge carriers called “holes”. The “P” stands for “positive”.

N type silicon occurs when group V elements like phosphorus, arsenic, or antimony are used to dope the silicon. This gives the silicon an abundance of negative charge carriers called “electrons”. Hence the “N” for “negative”.

This table summarizes the key differences:

	P type Silicon	N type Silicon
Dopant Atoms	Group III (boron, gallium, indium)	Group V (phosphorus, arsenic, antimony)
Major Charge Carriers	Holes (positive)	Electrons (negative)

So in essence, P type silicon conducts electricity in a positive way by moving holes, while N type silicon conducts via the movement of electrons.

Why both P type wafers and N type wafers are needed

The interesting thing about semiconductor devices is that they require both P and N type silicon to operate. Simply using one or the other is not enough to make transistors, integrated circuits, solar cells, etc.

This is because we need the interaction at the P-N junction, the boundary between the positive and negative silicon. The different properties on each side of the junction enable all kinds of useful applications.

For example, applying voltage across the P-N junction results in current flow, which is how diodes and LEDs work. And transistors rely on modulating the width of the P-N junction depletion region to switch current on and off, amplifying signals along the way.

So in summary, while P type and N type silicon wafers can conduct electricity on their own, combining them opens up vastly more possibilities. Almost all modern semiconductor electronics require both.

How P type silicon wafers are made

Producing monocrystalline silicon is an intricate process requiring high temperatures and systematic seeding and filtering procedures. But what really makes a silicon wafer P type is the precision doping techniques.

There are a few common ways to dope silicon with group III acceptor atoms:

• Doping during crystal growth: Adding boron or gallium impurities to the molten silicon as it is crystallizing into an ingot
• Thermal diffusion: Exposing the wafer surface to boron nitride or boron tribromide at over 1000°C to infuse atoms
• Ion implantation: Firing a beam of boron ions directly into the silicon lattice

Ion implantation tends to be the favored approach in advanced semiconductor fabs. It offers precise control over the doping concentration across very thin layers within the silicon crystal. Proper calibration is critical to optimize the positive charge carrier mobility.

How N type silicon wafers are produced

Much like P type wafer production, creating an N type silicon wafer starts with refining raw silicon into an ultra-pure monocrystalline form. The difference lies in which impurity gets embedded to enable negative charge carriers.

Common doping techniques for N type silicon wafers include:

• Phosphine gas diffusion: Exposing wafers to phosphine gas (PH3) at over 900°C evenly diffuses phosphorus atoms
• Liquid phosphorus diffusion: Dripping POCl3 liquid onto wafers and heating to ~1000°C
• Ion implantation: Firing phosphorus ions directly into the silicon to precisely control doping

Ion implantation often achieves the best results for N type wafers engineered for advanced electronics. Beam currents and acceleration voltages can be calibrated to generate very precise N type regions within the silicon for specialized applications.

Comparing P type silicon wafer vs. N type silicon wafer specs

While the doping process is what distinguishes P and N type wafers, the substrate specs also impact quality and performance. Electronics-grade silicon wafers should meet exacting standards like:

• Resistivity: A measure of charge carrier concentrations, directly related to doping levels
• Flatness: Minimal wafer warpage to enable lithography and interconnect uniformity
• Surface roughness: Smooth surfaces are vital for small node etch and deposition consistency
• Oxygen content: Effects formation of crystal defects that can degrade device performance
• Metallic impurities: Iron, copper and other metals influence carrier lifetimes

N type wafers tend to have higher resistivity than comparable P type. They also often are produced with slightly lower oxygen levels and metallic impurities. However, both P and N wafers for semiconductor device fabrication require tight control and metrology to verify all parameters are in spec.

Table: Example metrology data comparison of 300mm N vs P type silicon wafers

Parameter	N type wafer	P type wafer
Diameter	300 mm	300 mm
Crystal orientation	<100>	<100>
Dopant	Phosphorus	Boron
Resistivity	1-50 Ω-cm	1-30 Ω-cm
TTV	< 5 μm	< 5 μm
Site Flatness (SFQR)	< 70 nm	< 70 nm
Surface Roughness (RMS)	< 0.15 nm	< 0.15 nm
Oxygen Content	12-14 ppma	14-18 ppma
Iron Content	< 5 x 109 atoms/cm3	< 5 x 109 atoms/cm3

So while the doping elements make P type and N type what they are, wafer suppliers also have to tightly control all other attributes to produce devices reliably on the substrates. Matching client device requirements calls for monitoring and optimizing a variety of interdependent specifications simultaneously.

Why silicon wafer standards keep evolving

Semiconductor manufacturing has been on an accelerating pace of advancement for decades. The famous “Moore’s Law” predicted transistor densities would double every two years, which has held mostly true over 50 years later. This rapid progress forces wafer standards to continually evolve just to keep up.

Each chip generation with smaller feature sizes and more complex architectures levies tighter demands for purity, flatness, surface finishes, charge mobility and more. Wafer suppliers invest heavily in metrology, manufacturing tools and cleanrooms to meet these dynamic requirements.

Both device designers and wafer producers play crucial roles in each node evolution. Close collaboration lets foundries customize silicon properties precisely for leading-edge logic and memory chip fabrication needs.

For example, a GPU designing chipmaker might request custom 300mm N type wafers with targeted resistivity maximums and tighter metallic impurity allowances to boost electron mobility in certain critical areas. An experienced wafer partner can tailor ion implantation doping profiles to match precise specs.

These kinds of advances require billion-dollar investments into next-gen manufacturing. However, the potential performance and efficiency gains motivate pushing wafer standards into new territory with each progressive semiconductor node.

Key wafer characteristics for high performance devices

While meeting baseline flatness, cleanliness and purity standards is essential, additional wafer features determine suitability for bleeding-edge semiconductor manufacturing.

Some key silicon wafer metrics influencing modern high performance integrated circuits include:

Charge carrier mobility

Electron and hole mobility directly affect transistor switching speeds and therefore chip computing potential. Wafer partners can tune mobility via tailored doping profiles and minimizing defects.

Crystal originated particles (COPs)

Defects like COPs alter locally charged states in devices leading to current leakage or short circuits. Tight COP control is imperative below the 65nm node.

Edge placement error (EPE)

EPE indicates nano-scale mapping accuracy of features from mask to wafer. Advancements in exposure tools target sub-5nm EPE as chips dip below 10nm geometries.

Overlay accuracy

This reflects alignment precision of sequential lithography layers. Misalignments scramble intricate chip layouts, so wafer flatness and stability enables meeting single-digit overlay specs.

Warpage evolution

As reticles press nearer to wafers during exposure, tighter constraints on transient warpage defects become necessary. This motivates stiffer, thinner wafer materials less prone to distortion.

By optimizing these and other key parameters, wafer suppliers allow chipmakers to meet demanding performance requirements across logic, memory and advanced packaging.

Summary: why both P type and N type wafers remain essential

Silicon wafer technology has progressed enormously since the early days of computing, allowing today’s smartphones to outpace yesterday’s supercomputers. Yet performance gains never cease, with devices constantly pushing into smaller geometries and more complex 3D architectures.

One thing that hasn’t changed though across decades of evolution is the need for both P type and N type silicon wafers. These complementary substrates enable all modern semiconductor electronics via precision doping techniques. Wafer engineers continue innovating new methods for tightly controlling critical specifications as basis for groundbreaking high performance integrated circuits.

Through ongoing collaboration across the silicon supply chain, the capabilities of both P type and N type wafers steadily advance. Tight integration between chipmakers, equipment providers and wafer specialists allows standards to progress in concert with roadmaps like ITRS. This coordinated ecosystem fuels the exponential increases in computing power that transform entire industries and enhance every aspect of modern life.

So while end user gadgets come and go, relentlessly getting smaller, faster and smarter, their foundations in silicon technology remain. At the heart of it all are intrinsically simple yet amazingly complex P type and N type crystalline wafers, pushing electronics into the future one atom at a time.

FAQs

What are some common applications of P type silicon wafers?

P type wafers are extensively used in solar cells, LEDs, and as substrate material for microprocessors and ASICs. Their abundance of positive charge carriers makes them useful anywhere hole mobility is preferred.

What are some common applications of N type silicon wafers?

N type silicon wafers are widely used for building power devices like high voltage MOSFETs, IGBTs, rectifiers and converters. Their surplus electrons also make them suitable anywhere electron mobility is advantageous, like in specialized RF transistors, microwave components, and some sensors.

How are P type silicon wafers made conductive?

They are conductive as-made since the group III doping provides abundant holes as positive charge carriers. But for optimum conductivity, additional processing like thermal annealing, hydrogen passivation, or applying metal contacts and interconnect layers help maximize charge mobility.

How are N type silicon wafers made conductive?

Similar to P type, the group V doping itself generates ample negative electrons that allow conduction. Further steps like surface passivation, applying electrodes, or integrating with semiconductor devices optimize electron flow by reducing potential barriers at the interfaces.

What companies are the largest producers of silicon wafers?

The top seven silicon wafer companies globally based on total production capacity are Shin-Etsu, SUMCO, GlobalWafers, Siltronic, SK Siltron, Wafer Works, and FormFactor. However, many smaller specialized suppliers also participate in producing wafers used across the industry.